Senior Design and Verification Engineer

As a member of the dynamic multinational team, you’ll work side-by-side with some of the best minds and biggest brands in the semiconductor industry. You’ll help build innovative products for the artificial intelligence, automotive, HPC, data center and networking markets. In particular, you’ll work as part of a team contributing to our digital verification projects with our product development team. We are looking for a "hands on" active participant and technologist to provide expertise in digital ASIC verification. You will perform RTL verification using System Verilog and object oriented tests using UVM, write documentation, develop verification environments, test benches and verification components, verify design implementations, and develop test benches and test cases for simulation platforms according to design/architecture specification.

Other verification duties include:

● Architecting a System Verilog/UVM test environment

● Creating a stimulus and test plan to verify a design per its functional specification and applicable standards

● Designing and implementing UVM components using third-party VIP to verify components of the ASIC IP

● Performing code and test plan reviews

● Planning for, implementing, and analyzing functional coverage

● Scoping, planning, and tracking verification activities including test development, and test and coverage plan execution

● Designing and tracking multiple product regressions while succinctly and accurately reporting status

● Creating a UVM environment from scratch

● Reviewing standards updates to ensure test plan remains in compliance

● Debugging issues with the verification environment and tests

● Recreating field issues using the verification environment

We are looking for Engineers with knowledge of:

● Networking protocols - specifically as 802.3 (Ethernet) and related standards

● Highspeed protocols like PCIe, CXL

● Security algorithms used in networking and adjacent domains

● Previous Verification Background

● Forward Error Correction

● Technical leadership

● Verilog/System Verilog

● Test benches, UVM, OVM, VIP

● Creating UVM agents and environments from scratch

● Perl/Python or other scripting

● Unix/Linux scripting (perl, tcl, python, shell) with advanced debug skills

● Advanced debugging skills

● FPGA implementation knowledge a plus

● Tools: Cadence Incisive, Genus, Spyglass

Education Required: Bachelor or Masters Degree in Electrical and/or Computer Engineering Experience Required: Entry level – with relevant coursework

Salary: Market Compatible

Experience Required: Minimum 3-5 Years

Job Type: Full-time